Z-zero Launches v2018.1 of Z-planner and Z-solver
Redmond, Washington, December 31, 2018 – Z-zero announced today the second major release of its PCB stackup planning software products—Z-planner, for PCB stackup design and materials selection; and Z-solver, for quick, accurate impedance and insertion loss results.
“Survival in the world of high-speed design requires accurate prediction of electrical performance based on design and material properties. Z-zero’s focus on accurately modeling the detailed elements of PCB stackups is a valuable contribution to the industry,” said Dr. Eric Bogatin, industry pioneer and author of the popular text, “Signal and Power Integrity – Simplified” and co-author of the follow-on, “Principles of Power Integrity for PDN Design – Simplified: Robust and Cost Effective Design for High Speed Digital Products.”
Z-solver and Z-planner’s New Features in 2018.1
Bill Hargin, Director of Everything at Z-zero, noted that “this product release is primarily focused on accommodating feature and functionality requests from customers. 14 new features have been added along with 12 new laminate systems, as well as 121 bug fixes. We feel that this release has a good mix of our own innovation combined with helpful requests from our growing user community, and I’m excited to be shipping this so we can get to the rest of our development pipeline.”
2018.1 adds support for features requested by signal-integrity engineers, including unlimited single-ended and differential impedance classes and functionality for mitigating glass-weave skew (aka: fiber-weave effect). SI engineers also requested the ability to simulate signal-propagation speed and delay on signal layers, as well as the ability to perform what-if analysis of insertion loss.
Several hardware teams requested support for sequential lamination, including detailed support for modeling of sequentially-laminated prepregs—critical for impedance planning and signal-integrity simulation of sequentially-laminated outer-layer signals.
The 2018.1 release adds bidirectional Valor ODB++ support, and the ability to import additional PCB fabricator stackup formats that were requested by hardware OEMs.
New laminate libraries are provided, including materials from EMC (Elite Materials), ITEQ, Nanya Plastics, Panasonic, Park Electrochemical (Nelco), and TUC (Taiwan Union Corp.).
To assist with laminate selection, 2018.1 adds an automated Excel export of common material comparisons for material-selection support early in the design process. Filterable parameters include dielectric constant (Dk), dissipation factor (Df), glass-transition temperature (Tg), decomposition temperature (Td), z-CTE, xy-CTE, and other parameters.
Significant Benefits for Digital Hardware Engineering Teams
Most hardware designers are comfortable representing PCB stackups using spreadsheets, so Z-planner is architected to look and operate like one. The tool bridges the sizable gap between the spreadsheets many engineers and fabricators use to describe their stackups and the PCB signal-integrity world — with a super-short learning curve.
The 2017.1 release included an import/export interfaces for IPC-2581 and Mentor’s HyperLynx signal-integrity software, allowing users to bring legacy stackups into Z-planner, taking advantage of some of the additional features and functionality in Z-planner, including the 142-material library and awareness of glass styles, resin contents, pressed prepreg thicknesses, the frequency dependence of dielectric constants (Dk) and dissipation factors (Df), and automation of the PCB stackup design process. Engineering teams that are serious about signal integrity, crosstalk, and power integrity should find Z-planner to be an accuracy-increasing addition to their high-speed design flow — all bundled into a powerful, affordably priced, easy-to-use tool.
About Z-solver
Z-solver provides the most reasonably priced path to making what-if tradeoffs between Dk, Df, physical trace topologies, and spacing — with results that include single-ended impedance, differential impedance, propagation delay, loss as a function of frequency, and the effects of copper roughness.
About Z-zero
Z-zero, based in Redmond, Washington, develops PCB stackup planning and material-selection software for electronic-system design. For further information or to download a free evaluation of the software and stackup-design tutorial, please visit z-zero.com.