While writing this article, I’ve been thinking of places that skin appears in nature and pop culture. When I started writing, I flipped on Skinwalker Ranch on the History Channel for the first time as background noise, and they were talking about magnetic fields, current flow, and Tesla coils.

Skin is said to be the largest organ in the human body. It has multiple layers and some amazing properties. Galvanic skin response, used in lie detectors, measures changes in skin conductance caused by sweat-gland activity. I suppose you could call that a “skin effect” too.

It’s perfectly reasonable for engineers and PCB designers to ask, “Where should I focus my attention?” insofar as loss is concerned. In Signal and Power Integrity – Simplified,¹ Dr. Eric Bogatin points out five ways energy can be lost to the receiver while the signal is propagating down a transmission line:

1. Radiative loss
2. Coupling to adjacent traces
3. Impedance mismatches and glass-weave skew (the latter being my addition)
4. Conductor loss
5. Dielectric loss.

Each of these mechanisms reduces or affects the received signal, but they have significantly different causes and remedies. Plenty of articles over the years have discussed managing impedance and crosstalk, including ones I’ve written. I’ve also written about managing loss through dielectric-material selection and copper roughness, one of the two components of conductor loss. The other contributor to conductor loss is commonly known as skin effect.

From DC to about 100MHz, the bulk resistivity and, by extension, the series resistance of copper transmission lines are constant, and current flow is uniform across the entire cross-section. AC currents, on the other hand, take the path of lowest impedance at higher frequencies – traveling in a thin shell on the conductor’s surface toward the outside of the conductor.The result is an effective reduction in the trace cross-section. At high frequencies, the cross-section through which current will flow in a copper conductor is referred to as the skin depth, δ:

where

δ = skin depth, in µm
f = frequency, in GHz.

In copper, at 1GHz, the current in a transmission-line cross-section, for example, is concentrated in a layer about 2.1µm thick, on the perimeter or “skin” of the trace, shown graphically in FIGURE 1. At 10GHz, current flow concentrates in a layer of 0.66µm thick. Note: This relationship has nothing to do with trace width or any other parameter but frequency.

Signal resistance depends on the actual cross-section the current is flowing through. So, at higher frequencies, like the 10GHz frequency point where the skin depth is 0.66µm in Figure 1, resistance will increase with frequency. It’s important to note the only thing that’s changing to cause this increase in resistance is the cross-section through which the current is flowing.

FIGURE 2 illustrates the skin effect phenomenon for a 0.5-oz. symmetrical stripline trace at various frequencies. The top cross-section shows that at 70MHz current will flow through the entire cross-sectional area, as the skin depth still reaches the midpoint of the trace in the vertical. Skin depth, δ, is 7.9µm, half the thickness of half-ounce copper after processing. Resistance will be unaffected for half-ounce copper at this frequency, and currents will follow the path of least resistance.

The second image shows the same trace cross-section at 1GHz. Following the graph in Figure 1, the skin depth, δ, is 2.1µm. This is shown by the orange “skin” around the perimeter. At 1GHz, the blue area represents the remaining area where there is no current flow. Note the “current crowding” of high-frequency signal components on the top and bottom of the trace cross-section. Above the frequency at which skin effect kicks in – the “skin-effect onset frequency,” as some call it – signals follow the path of least inductance. (An entire article could be written on this subject alone.)

The third cross-section shows the skin depth at 10GHz for the same half-ounce trace. Note δ is reduced to 0.66µm, as is seen in the plot in Figure 1.

where

Loss_resistive= is resistive loss (attenuation),
Length = trace length in inches
w = trace width in mils
Z₀ = the single-ended impedance (ohms)
f = frequency (GHz).

Note that trace length, frequency and impedance are the biggest factors in this equation. Frequency and length increase loss, as you would expect, and impedance reduces it. Trace width pulls resistive loss down too, but both trace width and trace thickness in the vertical are factors in the denominator of the impedance relationship, reducing trace width’s impact on resistive loss. Thickness, which is a small value for signal layers whether 0.5 or 1.0-oz. copper is used, is a small factor compared to the others. As Figures 2 and 3 show, currents and electromagnetic fields crowd toward adjacent reference planes in the vertical, whether 0.5 or 1.0-oz. copper is used.

Let’s plug in some numbers for a 36″ backplane as an example. At 10GHz, a 50Ω stripline with a width of 4.9 mils will have an attenuation from the conductor of Loss_resistive equaling approximately (36)(10)^1/2/(4.9 x 50) = 0.46dB/in. Across the 36″ run length, it would be 16.7dB from resistive loss.

Reducing loss by increasing trace width is a commonly considered option for reducing resistive loss. Several years ago, I sat in on Lee Ritchey’s “Getting to 32GHz” workshop, and he had a few things to say on this subject that bear repeating.

Ritchey² mentioned that increasing trace width reduces impedance. Fair enough. He went on to say that to maintain the 50Ω single-ended impedance required for each line in a differential pair, the dielectric thickness needs to increase, increasing the overall thickness of the PCB, along with the cost due to the additional dielectric material. He pointed out dielectric loss dominates the loss problem for common laminates, and selecting a lower-loss dielectric provides more leverage than using wider traces to reduce skin-effect losses.

It’s pretty easy to show this with a good 2-D field solver, which we’ll do next, reusing our 36″, asymmetrical stripline backplane example above. For a 4.9-mil line width and 0.5-oz. copper, the insertion loss due to the skin effect (aka: resistive loss) is 0.35dB/in., as shown in FIGURE 4. While the results are in the same ballpark, the simulated resistive loss is a good bit lower than the calculated value above (0.46dB/in.). I have more trust for a field solver over the equation-based approximation, partially because the field solver represents a detailed model of Maxwell’s equations, but also due to its flexibility. A good 2-D field solver allows inclusion of dielectric loss and copper roughness in the same simulation. Adjustments between microstrip and both symmetrical and asymmetrical stripline configurations are automated in field-solver software as well.

Some may be confused into thinking an interrelationship exists between different types of loss – for example, between resistive loss and dielectric loss. Dielectric loss is tied to a dielectric material’s loss tangent, which is represented by tan(δ). No connection exists between the δ in tan(δ) and the δ in skin depth. And, if you look at the resistive loss equation above, there’s no connection between Loss_resistive and loss tangent or dissipation factor (Df).

Scanning the resistive loss equation cited above, we can see factors that relate to everything surrounding the trace, including Dk, which ties to Z₀, but not copper roughness or Df, as noted above. Contributions from each of these can be calculated or simulated separately and then summed together, as we’ll do in the example below.

Let’s say we’re starting from scratch on the backplane interconnect outlined above. We’ll assume all we know is it needs to be 50Ω, single-ended, 36″ in length, and we want to keep total loss at 20dB or lower (0.55dB/in.) to prevent excessive power consumption from transmitter pre-emphasis and the receiver’s equalization circuitry. Ignoring vias for this particular example, we’ll start with a symmetrical stripline with an initial dielectric height of 4 mils, a Dk of 3.6 and a Df of 0.005 at 10GHz. Ideally, we’d like the Dk to be even lower because it helps keep the board thickness and cost down and helps with loss. (Dk is in the denominator of the Z₀ relationship, and Z₀ is in the denominator of the loss relationship. As a result, there’s a direct connection between Dk and loss.) We’ll also say we would prefer 0.5-oz. copper because it’s less expensive, but we’re willing to consider 1-oz. copper. Copper roughness will start at R_z=5.0µm. (Note: Many equations regarding copper roughness use RMS roughness, which is a hard number to obtain from laminate and PCB fabricators, so I tend to use R_z, the peak-to-peak measurement, which is a rather easy number to obtain with a profilometer.)

FIGURE 6 shows the result, but in our initial swing at hitting 0.55dB/in. we are pretty far off. The copper roughness contribution alone is consuming most of our interconnect loss budget, and at 0.54dB/in. it’s more than twice the dielectric loss. We’ll start here first.

A good backplane fabricator can build PCBs with a roughness of 1.5µm on the “process” or prepreg side. Most hardware designers working on long, high-frequency backplanes are aware smooth copper comes at a price premium, so we’ll try R_z=2µm and R_z=1µm, respectively. An R_z roughness of 2µm brings us to a copper roughness loss of 0.11dB/in. and a total loss of 0.77dB/in. This is much better, of course, but we still have a good bit of loss to trim from our design, so it’s worth trying R_z=1µm copper. This brings us to 0.07dB/in. for copper roughness and a total loss of 0.73dB/in., as shown in FIGURE 7. Note the resistive loss from the skin effect didn’t change at all. As noted above, there’s no interrelationship between these two parameters.

Now we need to look at where we’re going to get the last 0.18dB/in. The resistive loss or skin effect looks like the biggest remaining contributor, so against my own best judgment from experience, I’ll go there next in this example. To hit 50Ω with this example required a trace width of 3.77 mils. That’s doable, but a bit on the aggressive side from a manufacturing standpoint and possibly from a resistive loss standpoint. Let’s bump that up by a mil and see if we can find a laminate construction with a lower Dk to help us hit our impedance target. A good number of materials have Dks in the 3.3 range with Df values at or below 0.005. FIGURE 8 shows that widening the trace by 1 mil only reduced resistive loss by 0.06dB/in., and we had to move to a thicker dielectric, 4.5 mils, to maintain our impedance target. As Ritchey mentions, this seems a less-than-optimal tradeoff.

This process may seem tedious, but no one said designing 36″ backplanes is easy. Nevertheless, spending a little time with a handy software tool can give you a feel for the tradeoffs. One advantage is you can try things almost as fast as you can think of them.

We’ve seen the physics of skin effect make it hard to affect. But before we rule out changing copper weight or trace width completely, I thought I’d pass along a tip I’ve learned through many hours of experimentation with the tradeoffs. As fine-tuning knobs for impedance and resistive loss, these two parameters are great, especially when working with a sharp pencil.

If you can make material and routing decisions like this early in the design process, you’ll avoid prototype surprises down the road or paying more than you need to for laminate systems that are overkill for a design. Making these choices early also allows you to avoid initial laminate lead times that can delay prototypes or early production. Because of prepreg shelf lives, fabricators only carry the laminates they know they can use within six months or less, so a just-in-time approach is usually followed. As with many other aspects of life, planning gives more options and fewer surprises. You can feed that expensive signal-integrity solution Dk and Df data from the actual laminate system you’re planning to use. Moreover, it may allow you to hold to NPI (new product introduction) schedules more consistently, while relieving some of the pressure you’ve been putting on PCB suppliers to make up for poor planning. Everyone wins!

I appreciate hearing from readers. Drop me an email if you read this far and found this article helpful!

1. Eric Bogatin, Signal and Power Integrity – Simplified, Pearson Education, 2010.
2. Lee Ritchey, “Getting to 32 Gb/s,” DesignCon Proceedings, 2018.

1. Brian Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Prentice Hall, 2000.